module display (
    clk, scan, d0, d1, d2, d3,
    a, b, c, d, e, f, g, pos
);

  // input
  input clk, scan;
  input[3:0] d0, d1, d2, d3;
  // output
  output reg a, b, c, d, e, f, g;
  output[3:0] pos;

  wire[3:0] din;
  wire[1:0] q;


  // 计数器（模4）
  counter_n #(.n(4), .counter_bits(2)) counterInst(
    .clk(clk), .en(scan), .r(1'b0), .q(q), .co()
  );
  // 4-1选择器
  mux_4to1 #(.counter_bits(4)) muxInst(
    .out(din), .in0(d0), .in1(d1), .in2(d2), .in3(d3), .addr(q)
  );
  // 2-4译码器
  decode decodeInst1(
    .din(q), .out(pos)
  );

  always @(*) begin
    case(din)
      4'b0000:  {a,b,c,d,e,f,g} = 7'b0000001;
      4'b0001:  {a,b,c,d,e,f,g} = 7'b1001111;
      4'b0010:  {a,b,c,d,e,f,g} = 7'b0010010;
      4'b0011:  {a,b,c,d,e,f,g} = 7'b0000110;
      4'b0100:  {a,b,c,d,e,f,g} = 7'b1001100;
      4'b0101:  {a,b,c,d,e,f,g} = 7'b0100100;
      4'b0110:  {a,b,c,d,e,f,g} = 7'b0100000;
      4'b0111:  {a,b,c,d,e,f,g} = 7'b0001111;
      4'b1000:  {a,b,c,d,e,f,g} = 7'b0000000;
      4'b1001:  {a,b,c,d,e,f,g} = 7'b0000100;
      default:  {a,b,c,d,e,f,g} = 7'b1111111;
    endcase
  end

    
endmodule